AMD Shows 256-Core Zen 6 EPYC Venice CPU at Advancing AI — SkimNews
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- AMD showcased its 6th-gen EPYC Venice CPU at the Advancing AI 2026 event in San Francisco's Moscone Center West, with the flagship pictured on a banner featuring 256 Zen 6 cores and 512 threads spread across eight CCDs (32 cores each) and two large I/O dies.
- EPYC Venice is the first HPC product to enter volume production on TSMC's 2nm process, which moves from FinFET to nanosheet (GAA) transistors and promises 10–15% higher performance at iso-power, 25–30% lower power at iso-performance, and up to 15% higher transistor density.
- AMD claimed its Zen 6 EPYC Venice chips deliver over 70% performance and efficiency improvement along with a >30% increase in thread density, with the chip supporting PCIe 6.0, UCIe, DDR5, and up to 16 memory channels on the new SP7 platform.
- EPYC Venice is positioned against NVIDIA's Vera Arm-based CPUs inside Vera Rubin NVL72 racks, with early AMD benchmarks claiming Venice extends a lead over Vera that Turin already held in agentic AI workloads.
- AMD's Helios AI racks pair the new EPYC Venice CPUs with Instinct accelerators, and a separate announcement at the show saw AMD land Anthropic in a 2GW Instinct MI450 deal backed by a $5 billion equity bet.
- The EPYC roadmap table shows Venice and Venice-Dense shipping in 2026 on 2nm at ~600W TDP, with a Zen 6+ EPYC Verano (EPYC 9007) following in 2027 on a still-TBD node.
Why it matters: By claiming a first-to-volume 2nm HPC chip and a 256-core flagship purpose-built for agentic AI, AMD is reframing the data-center AI race as CPU-versus-CPU inside GPU-heavy racks — directly challenging NVIDIA's Vera CPUs that anchor its Vera Rubin systems. If Venice's claimed >70% performance-and-efficiency gain holds, hyperscalers now have a credible x86 alternative for the orchestration and inference tiers where agentic workloads live, not just for GPU adjuncts.
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